用Verilog HDL设计1位全加法器的模块如下列代码。阅读后，指出哪一个说法不正确？module myadd (a, b, cin, sum, cout); //模块名，端口列表input a, b, cin; //输入端口声明output sum, cout; //输出端口声明reg sum, cout; reg m1, m2, m3; //变量声明always @ (a or b or cin) //always过程连续赋值beginsum = ( a^b ) ^ cin;m1=a&b;m2=b&cin;m3=a&cin;cout= ( m1|m2 ) | m3;endendmodule //模块结束语句